Tools produced by the group

EvoApproxLib - library of approximate circuits

The EvoApproxLib is the latest version of our library of approximate circuits with formally guaranteed error parameters. Compared to EvoAppro8b, this library contains substantially more circuits with various bitwidths. Moreover, signed as well as unsigned implementations are considered. Hardware as well as software models are provided for each circuit.

Go to tool »

EvoApprox8b - library of hundreds approximate 8b adders and multipliers

Approximate circuits and approximate circuit design methodologies attracted a significant attention of researchers as well as industry in recent years. In order to accelerate the approximate circuit and system design process and to support a fair benchmarking of circuit approximation methods, we propose a library of approximate adders and multipliers called EvoApprox8b. This library contains 473 Pareto optimal 8-bit approximate adders created from 13 conventional adders and 500 Pareto optimal 8-bit approximate multipliers created from 6 conventional multipliers. These implementations were evolved by a multi-objective Cartesian genetic programming. The EvoApprox8b library provides Verilog, Matlab and C models of all approximate circuits. In addition to standard circuit parameters, circuit error is given for seven different error metrics.

Go to tool » Download paper »


Cartesian genetic programming (CGP) is a branch of genetic programming in which candidate designs are represented using directed acyclic graphs. Evolutionary circuit design is the most typical application of CGP. This paper presents a new software tool CGPAnalyzer developed to analyse and visualise a genetic record (i.e. a log file) generated by CGP-based circuit design software. CGPAnalyzer automatically finds key genetic improvements in the genetic record and presents relevant phenotypes. The comparison module of CGPAnalyzer allows the user to select two phenotypes and compare their structure, history and functionality. It thus enables to reconstruct the process of discovering new circuit designs. This feature is demonstrated by means of the analysis of the genetic record from a 9-parity circuit evolution. The CGPAnalyzer tool is a desktop application with a graphical user interface created using Java v.8 and Swing library.

GitHub » Download paper »

Cartesian Genetic Programming Generator

In order to evaluate the fitness function the candidate solution has to be simulated. This step involves the interpretation of a CGP genotype for each vector. Since the fitness evaluation time dominates the time of whole evolutionary process in vast majority of problems and moreover a large number of evaluations is usually needed to achieve satisfactory result, it is important to simulate candidate solutions effectively.

In order to maximize the overall performance, we have replaced the interpreter with corresponding optimized native machine code that directly calculates response for a single training vector. The machine code is in linear form, i.e., without conditional branches hurting performance. We have developed a method which allows the users to significantly accelerate the evaluation of candidate solutions without having hardly any knowledge of assembly language or target machine code. Moreover, the integration of the machine code compiler requires modifying only a few lines of code.

As it can be seen on a simple case study CGP can process several times higher number of evaluations on the same machine introducing native evaluation. Even if we used optimized C implementation of CGP, we were able to evaluate more than five times higher number of candidate solutions using the same machine. Even when we used a highly optimized C implementation of the interpreted CGP, we were still able to evaluate more than five times greater amount of candidate solutions by using the native code version.

Details can be found in our paper Efficient Phenotype Evaluation in Cartesian Genetic Programming presented at EuroGP 2012. This paper contains evaluation in fixed as well as floating-point domain where one can achieve even better results.

Go to tool »

Image Database


Go to tool »


ZyEHW is a joint hardware-software project for evolutionary design in the Xilinx Zynq-7000 field-programmable gate array. It contains (1) the hardware descriptions of the evolutionary design framework implemented in the programmable logic, (2) the software for both ARM processors of the Zynq platform and (3) the software required for generating the inputs and processing the outputs of the evolutionary design framework. The evolutionary design framework is based on our developed architecture where the candidate solutions can be established and mutated by fine-grained partial reconfiguration of look-up tables. Our advanced control unit and the reduced routing ensures that six candidate solutions can be evaluated in parallel (in a XC7Z020 device) and at a very high operational frequency (a larger device would allow to evaluate even more candidate solutions in parallel). The program code is deployed into one of the processors of Zynq-7000 and the evolutionary design framework into its programmable logic. Evolutionary on-line synthesis is performed by the other available processor. The functionality is transferred from software into hardware on-line, during runtime. This approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line. Version v1.0 of ZyEHW includes the complete implementation of the case study for image filter evolution (noise filtering and edge detection).

GitHub »

© EHW@FIT 2005 - 2024