We have applied the evolutionary design method to evolve various circuits. In some cases evolved circuits are better than the best known conventional solutions (according to given critera). One patent was granted in 2013 (see Nonlinear image filter).

Image Filters

Evolved filters exhibit good filtering properties while the implementation cost (e.g. in the FPGA) is very low when compared to conventional solutions such as median-based filters.

• Impulse burst noise: AHS 2009 (with U. of Oslo), DATE 2010, AHS 2011, CEC 2011, Soft Computing J. (2013)
• Salt and Pepper Noise (high intensity): FPL 2007, ICES 2007
• Shot noise, edge detectors: CEC 2011, DDECS 2002 (Best Paper Award), NASA EH 2003
• Gaussian noise, random noise: EvoIASP 2002
• Dynamic noise: Mendel 2002
• see also Evolvable Components, Springer (Merit Award at Humies 2004)
• Reference implementations of conventional median filters DDECS 2008

Bio-signal classification and proceeding

• EEG signal classification: GECCO 2023
• Parkinson's disease EuroGP 2022, PPSN 2022, DDECS 2023, DATE 2023, EvoStar 2023

Evolutionary Logic Synthesis and Optimization.

• BDD-based fitness function for evolution of complex circuits: SSCI-ICES 2014
• SAT-based equivalence checking combined with simulation in the fitness function: EuroGP 2015 (Best Paper Award)
• SAT-based equivalence checking in the fitness function for evolution of complex circuits: GPEM 12(3) 2011, DATE 2011 (Silver Medal at Humies 2011), WCCI 2012, book chapter 2015
• Cartesian genetic programming really beats conventional synthesis tools in the case of "hard to synthesize" circuits: DDECS 2010 (with FIT CVUT Prague)
• Local vs. global optimization: ISVLSI 2022, DSD 2021, ISCAS 2019, EuroGP 2019, WCCI-CEC 2014, GECCO 2019, GPEM 21(3) 2020
• Small combinational circuits: Elektrorevue 2004, GECCO 2007, ICES 2010, GECCO 2010
• Semantic genetic programming GPEM 2021, GECCO 2020 (Best Paper Award Nomination), EuroGP 2019

Transistor level evolution, power consumption.

• Advanced transistor model: EuroGP 2015, EUC 2015 (power estimation], GECCO 2017
• Basic transistor model: ICES 2008
• FPGA Accelerator: SSCI-ICES

Benchmark Circuits for Diagnostics CAD tools

We evolved complex benchmark circuits (up to 1 M gates) with predefined testability.

• NASA EH 2005, DDECS 2006, TODAES 13(3), 2008 (Silver Medal at Humies 2008)
• Download FITTest_BENCH06 Benchmarks

Image Recognition

• Speed limit signs: PPSN 2004, ITS 2004 (with J. Torresen, University of Oslo)
• Low-cost number recognition: EuroGP 2014

Evolutionary Image Compression (with Ruben Salvador, Universidad Politécnica de Madrid).

• Evolution of Wavelet Transforms for Embedded Systems: EURASIP Journal on Advances in Signal Processing 2011, SPIE VLSI 2011, AHS 2010, DSD 2010, DCIS 2010, J. of Microprocessors and Microsystems
• Evolution of nonlinear predictors: Nostradamus 1999, FPL 2000

HW/SW Co-Design with EA.

• SSCI-ICES 2013, EuroGP 2014

Other Circuits.

• Bent and Hash functions GECCO 2019, Applied Soft Computing 2017, PPSN 2014 (Bronze Medal at Humies 2014), ICES 2015 , MENDEL 2016, GECCO 2016 , ICES 2016 , CEC 2017, CEC 2017, GECCO 2017, AHS 2018, EuroGP 2018, EuroGP 2019, CEC 2020
• Cryptographics functions CEC 2020
• Multiple Constant Multipliers: ICES 2008, Mendel 2012
• Gate-level evolution of FIR and IIR filters: EvoHOT 2006
• Median circuits: EvoHOT 2004
• Module Selection Problem in High-Level Synthesis: Mendel 2002
• Cryptographic primitives testing: GECCO 2018 , IEEE Tr. VLSI 2019
• Quantum computing SSCI 2020
• Branch Predictors: GECCO 2008
• Application protocol classification in FPGA: EvoComnet 2015, Applied Soft Computing 2016

We have applied the evolutionary design as a systematic design method to create approximate circuits.

• Neural networks and deep learning DATE 2020 (GitHub), IEEE Tr. VLSI 2020, ICCAD 2019 (GitHub), DATE 2019 (GitHub), ICCAD 2016 (with Purdue University, IN, USA), ISVLSI 2017 (with TU Vienna), GlobalSIP 2017, IEEE Access 2021, IEEE JETCAS 2023 (GitHub)
• Synthesis for FPGAs DDECS 2021, DAC 2020, FPL 2016, ICES 2016
• Multipliers, median circuits and sorting networks AICAS 2020 (Best Paper Award Nomination), Book chapter - Springer 2014, DATE 2019, IEEE Tr. VLSI 2018, ICECS 2018, AHS 2018, PATMOS 2016, Genetic programming and Evolvable machines 2017, Radioengineering 2017, IEEE Tr. on Evol. Comp 2015 (Golden Medal at Humies 2015))
• Adders, multipliers and combinational circuits: student paper DDECS 2022 (Best Paper Award), ISVLSI 2022, GECCO 2018, EuroGP 2016 (Best Paper Award Nomination), SSCI-ICES 2013 (Best Paper Award Nomination), GPAW DATE 2017 (see Tools; Best IP award), Applied Soft Computing (95) 2020, IEEE JETCAS (10) 2020, Swarm and Evolutionary Computation 2021
• Fault tolerance IEEE Tr. on Reliability 2016 (with Universidad Carlos III de Madrid), Microelectronics Reliability, 2023
• Multiobjective approach: DAC 2019 (with TU Wien), EuroGP 2015, DTIS 2016, High level synthesis ICES 2016 , DDECS 2013, Book chapter - Springer 2014
• Parallel multiobjecive approach: GECCO 2015
• The impact of error metrics and representations SMC 2023, DDECS 2014, IET CDT 2018, Inspired by nature 2018, Inspired by nature 2018
• Formal methods in fitness: IEEE Access 2019, VLSI-Test Symp. 2018, WAPCO 2016, GECCO 2015, Genetic programming and Evolvable machines 2016, DATE 2017, ICCAD 2017, SAT 2020, DSD 2022, DATE 2024
• Approximate SW for Embedded Systems: GECCO-GI 2015
• Surveys and tutorials: WAPCO 2015, WAPCO 2016, DDECS 2016, DDECS 2017, Journal of Ingtegrated Circuits 2021, Handbook of Computer Architectures (book) 2021, ETS 2021, Inexact Arithmetic Operators (book chapter) 2022, DDECS 2023

• Optimization of neural networks accelerators: IEEE Tr. VLSI 2021, DATE 2020, ESWeek 2020, DDECS 2024 (Best Paper Award), Neural Computation 2024
• Neuroevolution: Genetic programming and evolvable machines 2022, IEEE Access 2022, IEEE Tr. CAD 2021, EuroGP 2021, ICCAD 2020 (Best Paper Award Nomination), TPNC 2019, DDECS 2023, CEC 2024

We have developed the concept of Virtual Reconfigurable Circuits (VRC) for real-world applications of evolvable hardware in FPGAs.

• Accelerator for image filter evolution - speedup 170 wrt PC (EA in PowerPC, multiple VRCs): MEMICS 2009 (Best Paper Award), CaI 29(6), 2010
• Accelerator for image filter evolution - speedup 44 wrt PC (EA in PowerPC, 1 VRC): IJICA 1(1), 2007, AHS 2007 (analysis of mutation operators and pseudorandom generators)
• Accelerator of CGP (EA in PowerPC, 1 VRC): EuroGP 2008 (Best Paper Award Nomination)
• Accelerator for image filter evolution (EA in HW, 1 VRC): Hindawi's book chapter, ICES 2005
• Accelerator for sorting network evolution (EA in HW, 1 VRC): ICES 2005
• Accelerator for combinational circuit evolution (EA in HW, 1 VRC): DDECS 2004, NASA EH 2004, CaI 23(5), 2004

Analysis of the VRC concept

• Comparison with DPR: FPL 2012
• Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures: EvoHOT 2008 (Best Paper Award Nomination)
• Evolutionary Functional Recovery in Virtual Reconfigurable Circuits: ACM JETCS 3(2), 2007, ACM CF 2006
• Evolvable IP cores: NASA EH 2003
• Introduction of VRCs: ICES 2003 (Best Paper Award), DDECS 2000
• see also Evolvable Components (Springer)

Utilization of Dynamic Partial Reconfiguration (with CEI, Universidad Politécnica de Madrid)

• Processing Array: AHS 2011a, AHS 2011b, IEEE Tr. on Computers 2013
• Fault tolerance issues: Reconfig 2011

Accelerators based on the Xilinx Zynq chip (with DPR)

• Basic version: SSCI-ICES 2013, AHS 2013 (Best Paper Award)
• With optimized DPR: ICES 2014, ACM TRETS 2015
• On-line synthesis of accelerators for video: FPL 2014

• Xeon Phi - Bent functions: MEMICS 2015
• GPU - Evolution of Cellular Automata: FC 2009 (Best Paper Award), IJAS 3(1)

We have devoloped first reconfigurable polymorphic ASIC (REPOMO32), implemented several methods for synthesis of polymorphic circuits and proposed several new applications of polymorphic electronics.

• Polymorphic ASIC REPOMO32: WEAH 2009, (analysis of various architectures: AHS 2008 , IASTED CI 2006 )
• Synthesis of polymorphic circuits: EvoHOT 2005 (Best Paper Award), DDECS 2005, CEC 2006, CEC 2009, JMVLSC 17(6) 2011, DATE 2012, on transistor level: ICES 2016
• Polymorphic image filters: DATE 2012, WCCI 2012
• Polymorphic FIR filters: AHS 2009
• Self-checking circuits: DDECS 2007, ICES 2007
• Reduction of test vectors volume: DDECS 2008, JUC 4(2), 2008, ICES 2010
• Analysis and measurement of polymorphic gates: AHS 2006, DDECS 2006, ECS 2007, IOLTS 2008, DDECS 2010, DDECS 2011 (high temperatures), DSD 2011 (low temperatures), DDECS 2012
• Polymorphic Cellular Automata and Self-replication: JCA 6(4) 2011
• Unclonable chip ID on REPOMO32: J. of ITC 2013
• Survey: book chapter

We have introduced non-trivial mappings between genotypes and phenotypes to overcome the scalability problems of evolutionary design. One approach uses an instruction-based development, another one cellular automata.

• Cellular automata-based development: ICES 2008, AHS 2008, CEC 2009, GECCO 2009, AHS 2009, ICES 2010, ACRI 2012, WCCI 2012, SSCI-ICES 2013, CEC 2013, WCCI-CEC 2014, ICES 2015, ECTA 2015, IEEE Tr. on Evolutionary Computation (Silver Medal at Humies 2016), GECCO 2016, ECTA 2016 (Best Paper Award), Computational Inteligence 2017, GECCO 2019, Mendel 2019, Computational Intelligence 2019, CEC 2020
• Growing multipliers: AHS 2007, ICES 2007, JKBIES 12(3) 2008
• Growing arbitrarily large sorting networks: CEC 2021, IEEE Tr. EC 2020, SOFSEM 2004, GENP 6(3) 2005 (Honorable mention at Humies 2005)
• Growing polymorphic circuits: GECCO 2005 - workshop
• A formal proof that evolved constuctor for sorting networks is general: TECT 15(10), 2006
• The role of environment: Mendel 2010
• Ant colonies optimization: MENDEL 2019

Miller J. F. (ed.): Cartesian Genetic Programming, Springer 2011 - see chapters on circuit evolution, image processing and CGP in FPGA.

• Parallel implementations: GECCO 2014
• Coevolution in CGP: Evolutionary Computation 2018, SSCI-ICES 2018, EuroGP 2015, SSCI-ICES 2014, EuroGP 2012 (symbolic regression), PPSN 2012 (image filter design), ECAL 2013 (FPGA accelerator), EuroGP 2016 (plastic fitness predictors)
• Precompilation for a fast fitness evaluation: EuroGP 2012
• Evolution of iterative algorithms: KES 2011
• A new selection strategy: ICES 2010, GECCO 2010
• ALPS in CGP: EuroGP 2009
• Does crossover work in CGP? EuroGP 2007, EuroGP 2018
• CGP Visualisation GECCO 2016

• Fault tolerance in cellular systems: IOLTS 2000, UC 2011, NaBIC 2011, J. of Nat. Computing 2012
• Parallel GA for CellMatrix: ESM 2001

• Evolutionary computation in the physical world: ACM Ubiquity 2013
• Evolved Computing Devices and the Implementation Problem: Minds and machines 17(3), 2007, KUZ 2007 (in Czech)
• Evolvable systems - models and super-Turing behaviors: JNC 3(3), 2004, EuroGP 2003, E-ISCI 2002
• see also Evolvable Components (Springer)

• CA-based Microscopic Traffic Simulation: IV 2011
• Evolutionary calibration of CA-based Microscopic Traffic Simulation: ACRI 2012, ITSC 2012, Journal of CA
• GPU accelerators: Mendel 2011
• Estimation of traffic density map: ITSC 2012
• Multiobjective sensor selection: PPSN 2014, SSCI-CIVTS 2014, ITSC 2015

• Evolvable Hardware and evolutionary circuit design: ECBS 2004, AHS 2006, GECCO 2007, JAMRIS 3(2), 2009, UC 2009, GECCO 2011, SPIE VLSI 2011, Handbook of natural computing 2012
• In Czech: Elektrorevue 1999, Vesmir 81(7) 2002, Vesmir 84(1) 2005, Automa 1/2010, Umela inteligencia a kognitivna veda 2010

(with P. Svenda and V. Matyas, FI MU Brno)

• Evolutionary Design of Secrecy Amplification Protocols for Wireless Sensor Networks: WiSec 2009, EuroGP 2012

(with NASA JPL)

• Low temperature experiments: ICES 2005, Springer's book chapter 2006
• Flip-flops: EH 2005
• Controllable oscillators: ICES 2005