Download dataset as ZIP
CIRCUITS AND THEIR PARAMETERS
GIT (v1.0)

The EvoApproxLibLITE is the lightweight version of our library of approximate circuits with formally guaranteed error parameters. Hardware as well as software models are provided for each circuit.

Circuit name MAE WCE MRE EP power area Download model
mul12u_1BG [1] 0.00 % 0.00 % 0.00 % 0.00 % 1.157 1605.0 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_08N [1] 0.0000054 % 0.000006 % 0.00038 % 87.50 % 1.156 1598.9 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2EC [2] 0.0000075 % 0.00003 % 0.00062 % 50.00 % 1.152 1584.8 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2ED [2] 0.000025 % 0.0001 % 0.0019 % 68.75 % 1.142 1556.7 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2EF [2] 0.00019 % 0.00077 % 0.012 % 89.06 % 1.090 1469.4 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2EH [2] 0.0011 % 0.0046 % 0.057 % 96.48 % 1.009 1337.0 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_0UD [1] 0.0058 % 0.025 % 0.30 % 99.99 % 0.817 1131.5 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2DH [2] 0.073 % 0.29 % 1.67 % 99.84 % 0.511 768.7 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_2CS [2] 0.48 % 1.90 % 7.43 % 99.94 % 0.237 461.3 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_33E [2] 3.02 % 12.06 % 26.71 % 99.95 % 0.055 167.5 Verilog PDK45Verilog fileC fileMatlab MEXPython PYX
mul12u_35V [2] 18.74 % 74.95 % 87.98 % 99.95 % 0.0003 2.3 Verilog fileC fileMatlab MEXPython PYX

Reported error parameters: MAE - Mean Absolute Error (Mean Error Magnitude), WCE - Worst-Case Absolute Error (Error Magnitude / Error Significance), MSE - Mean Squared Error, MRE - Mean Relative Error (Mean Relative Error Distance), WCRE - Worst-Case Relative Error, EP - Error Probability (Error Rate)  |  Reported design parameters: power - power consumption in mW, area - area on the chip in um2, dly - delay, all values obtained using Synopsys DC (45 nm PDK, 1 V, 25 ℃)  |  Error parameters marked by were verified using a formal technique analyzing all possible input combinations. There is a formal guarantee that the error is not worse than the shown value. The exact values are included at the beginning of each C file and Verilog file.

COMPARISON

Comparison with the complete EvoApproxLib dataset on various metrics. The first plot shows the performance wrt. the parameters used for pareto filtration. The black dots are the circuits included in this dataset. The blue dots are parameters of the circuits included in the full version of EvoApproxLib. Note that the parameters of the accurate implementation shown in the figure correspond with those exhibiting the lowest power consumption.

REFERENCES
  1. V. Mrazek, Z. Vasicek and R. Hrbacek, Role of circuit representation in evolutionary design of energy-efficient approximate circuits in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018.
  2. V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018.


Evolvable hardware group

Faculty of information technology
Bozetechova 2, Brno 612 66
Czech Republic

Links

EvoApprox8B (deprecated) EvoApproxLibLITE