The basic library of approximate circuits
CIRCUITS AND THEIR PARAMETERS
The EvoApproxLibLITE is the lightweight version of our library of approximate circuits with formally guaranteed error parameters. Hardware as well as software models are provided for each circuit.
| Circuit name | MAE | WCE | MRE | EP | power | area | Download model |
|---|---|---|---|---|---|---|---|
| add8s_9CT [1] | 0.00 % | 0.00 % | 0.00 % | 0.00 % | 0.034 | 70.4 | Verilog fileC filePython PYX |
| add8s_7HJ [1] | 0.39 % | 0.78 % | 2.62 % | 50.00 % | 0.033 | 64.8 | Verilog fileC filePython PYX |
| add8s_7VE [1] | 0.78 % | 1.56 % | 4.35 % | 49.74 % | 0.032 | 71.8 | Verilog fileC filePython PYX |
| add8s_7ER [1] | 1.41 % | 3.91 % | 8.59 % | 83.20 % | 0.027 | 55.8 | Verilog fileC filePython PYX |
| add8s_7EQ [1] | 2.50 % | 5.47 % | 18.19 % | 87.50 % | 0.025 | 57.3 | Verilog fileC filePython PYX |
| add8s_7K3 [1] | 3.75 % | 9.38 % | 26.40 % | 93.75 % | 0.021 | 48.3 | Verilog fileC filePython PYX |
| add8s_7M8 [1] | 7.97 % | 19.53 % | 61.40 % | 96.88 % | 0.016 | 39.4 | Verilog fileC filePython PYX |
| add8s_7QY [1] | 12.27 % | 33.59 % | 75.00 % | 98.52 % | 0.012 | 32.9 | Verilog fileC filePython PYX |
| add8s_7FP [1] | 18.28 % | 54.69 % | 67.56 % | 98.52 % | 0.0063 | 26.8 | Verilog fileC filePython PYX |
| add8s_7P0 [1] | 44.45 % | 100.00 % | 99.98 % | 99.48 % | 0.000 | 0.0 | Verilog fileC filePython PYX |
Reported error parameters: MAE - Mean Absolute Error (Mean Error Magnitude), WCE - Worst-Case Absolute Error (Error Magnitude / Error Significance), MSE - Mean Squared Error, MRE - Mean Relative Error (Mean Relative Error Distance), WCRE - Worst-Case Relative Error, EP - Error Probability (Error Rate) | Reported design parameters: power - power consumption in mW, area - area on the chip in um2, dly - delay, all values obtained using Synopsys DC (45 nm PDK, 1 V, 25 ℃) | Error parameters marked by were verified using a formal technique analyzing all possible input combinations. There is a formal guarantee that the error is not worse than the shown value. The exact values are included at the beginning of each C file and Verilog file.
COMPARISON
Comparison with the complete EvoApproxLib dataset on various metrics. The first plot shows the performance wrt. the parameters used for pareto filtration. The black dots are the circuits included in this dataset. The blue dots are parameters of the circuits included in the full version of EvoApproxLib. Note that the parameters of the accurate implementation shown in the figure correspond with those exhibiting the lowest power consumption.
REFERENCES
- V. Mrazek, L. Sekanina, Z. Vasicek Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020